MICHAEL B HEALY
Quantum Computing Researcher
BIO
I am a systems researcher and Computer Engineer with a focus on compilers for quantum computing. I have done work in microprocessor design and simulation, with a special focus on early-design stage exploration and memory systems. I did my PhD research in physical design and physical design automation, performance simulation, and physical simulation.
I have worked for 10 years at IBM Research, where I have gained a deep experience with the memory subsystem and memory technologies, before moving onto the Cloud Infrastructure area, and then to quantum computing. I am something of a generalist, with knowledge in a wide range of areas. I always love diving into a new topic.
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My most used programming language is C++, but I am familiar with Perl and Python, and have been exposed to many others including Ruby, Go, TCL, Java, BASIC, and Scheme, as well as a number of scripting languages such as Ansible and Terraform.
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MY WORK
QUANTUM COMPUTING
September, 2020 - Present
I am currently working to develop a compiler system for supporting classical control flow in the execution of quantum algorithms in IBM's next-generation quantum computer architecture.
CLOUD INFRASTRUCTURE
2019 - 2020
Evaluated the performance impact of Optane Persistent Memory on etcd distributed key-value store and Kubernetes for use in cloud control plane (Blog Post)
Created automation for the deployment of a cloud-bursting architecture from on-premise LSF computing clusters based on Ansible and Terraform
Set up SPEC Cloud IaaS 2018 benchmark suite on IBM’s Gen2 VPC Cloud
SYSTEMS ARCHITECTURE
2013 - 2019
General focus on server memory subsystems and 3D stacked memory.
Technical co-lead of the memory tasks and subcontracts for the DoE PathForward research contract awarded to IBM covering approximately $6M in revenue. (2017 – 2020)
Developed detailed work plan and led research and writing of the memory-system task reports for the DoE FastForward2 contract awarded to IBM. (2014 – 2016)
Identified a lack of memory controller modeling in existing memory timing simulators. Led a team of 2 post-docs to develop and release a new open-source memory system simulator (CramSim) for both IBM-internal and academic use that puts more focus on the memory controller (2015 – 2019)
Responsible for the DRAM timing model of production memory system simulator. Executed a complete rewrite of the model to enable support of advanced features for next-generation (DDR5, 3DS) memories (2013-2016)
Assisted with the development of IBM’s vision for the DDR5 and HBM 2E/3 JEDEC memory standards and worked with the JEDEC committees responsible for their implementation. (2013 – 2019)
DESIGN AUTOMATION AND SYSTEMS ARCHITECTURE
2010 - 2013
Extensive creation and use of early-design stage physical design tools for microarchitectural exploration of IBM’s server microprocessors, including floorplanning, thermal, power-grid, and TSV routing analysis. (2010 – 2012)
Made several significant updates to IBM-internal physical design and performance analysis tools, including power-grid simulators, system bus and memory subsystem performance simulators, and created analytical models for performance projection. (2011 – 2013)
Corrected the DRAM performance model in IBM’s in-house system bus and memory subsystem simulation framework, performed studies projecting the impact of DDR4 timing parameter scaling, and explored various methods and configurations minimizing performance degradation. (2012 – 2013)
SELECTED PUBLICATIONS
See my Google Scholar page for the full list
I have over 31 issued patents and 28 refereed conference and journal papers
April, 2020
Michael B. Healy and Seetharami Seelam, IBM Cloud Blog
October, 2019
TOUCHÉ: TOWARDS IDEAL AND EFFICIENT CACHE COMPRESSION BY MITIGATING TAG AREA OVERHEADS
Seokin Hong, Bulent Abali, Alper Buyuktosunoglu, Michael B. Healy, and Prashant Nair, in IEEE/ACM International Symposium on Microarchitecture, pp. 453-465.
October, 2018
DUPLICON CACHE: MITIGATING OFF-CHIP MEMORY BANK AND BANK GROUP CONFLICTS VIA DATA DUPLICATION
Ben C. P. Lin, Michael B. Healy, Rustam Miftakhutdinov, Philip Emma, Yale Pat, in IEEE/ACM Symposium on Microarchitecture, pp. 285-297.
October, 2017
CRAMSIM: CONTROLLER AND MEMORY SIMULATOR
Michael B. Healy, Seokin Hong, in International Symposium on Memory Systems, pp. 83-85.
August, 2014
3-D STACKED MULTIPROCESSOR STRUCTURES AND METHODS TO ENABLE RELIABLE OPERATION OF PROCESSORS AT SPEEDS ABOVE SPECIFIED LIMITS
Alper Buyuktosunoglu, Philip G Emma, Alan M Hartstein, Michael B Healy, and Krishnan Kailas, US Patent 8,799,710, 2014.
My first published patent!
